Ferroelectric material exhibits a hysteresis characteristic and is capable of retaining polarization states even when power is removed from the material. Ferroelectric thin film capacitors have been used as bit storage components. FIG. 1 shows a graph for illustrating a hysteresis characteristic curve of conventional ferroelectric film.
There are two available structures for conventional ferroelectric memory cells. FIG. 2 is a circuit diagram showing a conventional 2T2C ferroelectric memory cell, which is composed of two MOS transistors and two storage capacitors 20 and 21. FIG. 3 is a circuit diagram showing a conventional 1T1C ferroelectric memory cell, which is composed of one MOS transistor and one storage capacitor 30.
Using the 2T2C ferroelectric memory cell structure, any reference cell is not needed in Write/Read operations because one-bit information comprised of a series of digits 0 and 1 is read from and stored into two storage capacitors 20 and 21 through a bit line BL and a complimentary bit line BL. But, since two storage cells are needed in order to store one-bit information, the density of integration is lower than conventional 1T1C structure.
As shown in FIG. 3, cell structure of the 1T1C ferroelectric memory is similar to conventional DRAM (dynamic random access memory). But reference cells are needed to read information from a ferroelectric capacitor 30.
FIG. 4 is a circuit diagram showing a structure of conventional 1T1C ferroelectric memory cells. When one of word lines WL.sub.0 through WL.sub.1 connected to the memory cells is selected, one of word lines RWL.sub.0 and RWL.sub.1 connected to the reference cells has to be selected by the following rule. If an even numbered memory cell word line WL.sub.0, . . . or WL.sub.n-1 is selected, complimentary bit lines (BL) 41a and 42a connected to the memory cells associated with the selected word line WL.sub.0, . . . or WL.sub.n-1 are activated depending on the charge of each storage capacitor Cs. At this time, one reference cell word line RWL.sub.1 has to be selected to supply the reference voltage to bit lines (BL) 41b and 42b depending on the charge of each reference capacitor Cr. Each sense amplifier 41 (or 42) compares voltage levels of a pair of bit lines 41a and 41b (or 42a and 42b), and then amplifies the voltage difference in order to read and determine whether the information stored in each memory cell is "1" or "0".
On the other hand, if an odd numbered memory cell word line WL.sub.1, . . . or WL.sub.n is selected, bit lines (BL) 41b and 42b connected to the memory cells associated with the selected word line WL.sub.1, . . . or WL.sub.n are activated depending on the charge of each storage capacitor Cs. At this time, the other reference cell word line RWL.sub.0 is selected to supply the reference voltage to complementary bit lines (BL) 41a and 42a depending on the charge of each reference capacitor Cr. Each sense amplifier 41 (or 42) compares voltage levels of a pair of bit lines 41a and 41b (or 42a and 42b), and then amplifies the voltage difference in order to read and determine whether the information stored in each memory cell is "1" or "0".
Therefore, whenever any one of the memory cell word lines WL.sub.0 through WL.sub.n is selected, one of the reference cell word lines RWL.sub.0 and RWL.sub.1 is selected, and then all of the reference cells associated with the selected word line RWL.sub.0 or RWL.sub.1 are activated. It is not required, however, that all of the sense amplifiers 41 and 42 are operated to obtain the voltage difference. This unnecessary activation of reference cells increases fatigue accumulated in the reference capacitor Cr that is a ferroelectric capacitor, and then distortion occurs in the hysteresis characteristic curve as shown FIG. 1. This results in deterioration of the ferroelectric film's lifetime. Lifetime of ferroelectric film is approximately 10.sup.12 .about.10.sup.15 cycles.
In the structure of conventional ferroelectric memory cells, reference cells experience more voltage cycles than storage cells Cs and therefore the overall lifetime of the memory is significantly reduced.